The present invention relates generally to the field of microelectronic circuit fabrication, more specifically to fabrication of flash memory microelectronic circuits, and most specifically to forming test structures on a microelectronic flash memory to facilitate measurement of the standby current of the finished flash memory chip.
Flash memory chips generally are formed with an array of memory cells centrally located and adjoined by memory cell periphery transistors (forming a control circuit) on one or more sides of the array. As flash memory technology progresses, the memory density and speed become higher and higher. The control circuit becomes more and more complex with the use of low voltage peripheral transistors for high speed core memory cell control. The peripheral transistors have to employ thin gate oxide and short channel dimensions, and as a result, the short channel effect becomes a major concern, affecting control of the off-state leakage currents. In standby mode, the leakage current induced by these low voltage peripheral transistors can cause the flash memory chip standby current to go beyond the design limit and cause excessive power consumption and reduce the product yields. In order to correlate product standby current with periphery transistors for chip development, there is a need to implement an effective means of measuring the chip standby current.
The present invention is a microelectronic test circuit structure for simulating and measuring transistor leakage current contributed by the low voltage peripheral transistors which occurs in standby mode. One or more test circuit structure or structures are formed on the chip during the manufacturing process for the operating device. The test structure may be located within or adjacent to the operational device(s) on the chip. The present invention provides surrogate test devices within or outside of operational circuit devices to measure parameters such as currents or voltages which are representative of those present at or created by operational circuit components, without the need for introducing special test points at the operational component, thereby eliminating the possible introduction of potential defect sources at the operational component. Additional test structures having other channel widths may be simultaneously included for engineering or testing purposes. Additionally, the test structure can also be designed for simulating other types of transistors, including intrinsic NMOS transistors, Z-type NMOS transistors and high-voltage transistors. The test circuit structure may also be modified to include diode or capacitor type protection.
The exemplary test circuit transistor structure of the present invention comprises a wide gate, finger-type transistor arrangement with minimum channel gate length (L). The channel gate width (W) of this finger-type transistor arrangement is designed to be equal to the estimated total gate widths of the periphery transistors of that type. For example, there typically are two types of periphery transistors, commonly referred to as low voltage NMOS and low voltage PMOS transistors, each having a gate width ranging from 1.6 Am to 340 Am. Each of these types of periphery transistors can have a total channel width (W) in the range of approximately 1.0 xcexcm to approximately 150,000 xcexcm on the chip. This large channel gate width variation can be used to generate standby current in the standby mode. The gate width of the test circuit transistor structure of the present invention is preferably large enough to represent the total widths of the periphery circuit transistors within the flash memory chip device. The invention implements one low voltage NMOS finger-type transistor and one low voltage PMOS finger-type transistor to simulate the standby current contribution from the corresponding multitudes of the two types of periphery transistors in the flash memory chip device. Regular electrical tests such as current-voltage tests can then be applied to the test structure, thus providing information on the correlation of the actual product standby currents with single transistor off-state leakage currents.